Short answer

Adopt a strategy of building verification environments with reusability as a core principle, enabling components to be leveraged across multiple projects and design stages to accelerate development and reduce costs.

Field: Commercial Production
Source: International Journal of VLSI Design & Communication Systems (2015)
Method: Methodology Development and Case Study
Evidence: Strong effect

Implementing a reusable test bench methodology significantly reduces the time and cost associated with System on Chip (SOC) verification, a critical bottleneck in product development. This commercial production research insight is drawn from a 2015 study published in International Journal of VLSI Design & Communication Systems. Using Methodology development and case study, researchers explored how this design variable affects real-world outcomes. The key design takeaway: Adopt a strategy of building verification environments with reusability as a core principle, enabling components to be leveraged across multiple projects and design stages to accelerate development and reduce costs.

Study

Commercial ProductionHigh ImpactStrong effect

Reusable test bench methodology slashes SOC verification time by up to 75%

Implementing a reusable test bench methodology significantly reduces the time and cost associated with System on Chip (SOC) verification, a critical bottleneck in product development.

International Journal of VLSI Design & Communication Systems · 2015

Key Findings

01Verification effort can account for 75% of the total design effort for complex SOCs.
02A reusable test bench methodology can significantly decrease time to market.
03Code reuse across design levels (sub-block, block, top-level) leads to cost savings.
04Intelligent verification approaches are crucial for managing complexity.

Application

Design takeaway

How to apply

When designing a new complex system, consider creating a library of standardized verification modules that can be easily integrated and adapted for different sub-systems and future projects.

Project actions

01When designing a product, think about how you will test it. Can parts of your testing setup be used again for other parts of the design or even for future projects?
02Consider how to make your design documentation clear so that others can understand and reuse your testing methods.

Method & Evidence

AimHow can a reusable test bench methodology be developed to decrease the time to market and cost for complex System on Chip (SOC) devices?

MethodMethodology Development and Case Study

ProcedureThe research proposes an advanced reusable test bench development technique for SOC verification. This involves designing verification components that can be reused across different levels of abstraction (sub-block, block, and top-level) and for various IP configurations, thereby facilitating code reuse and reducing manual effort.

ContextSemiconductor industry, System on Chip (SOC) design and verification

Variables

IVImplementation of a reusable test bench methodology

DVTime to market, Verification effort/cost

CVComplexity of SOC, Design IP configurations

Strengths & Limitations

Strengths

+Addresses a critical bottleneck in complex system development.
+Provides a practical strategy for cost and time reduction.
+Emphasizes the importance of methodology over just language.

Limitations

The complexity of the system being designed will influence how easily verification components can be reused. Not all verification tasks are equally amenable to reuse.

Reliability & validity

The findings are based on industry expert consensus and the proposed methodology. Empirical validation through case studies with quantitative data on time and cost savings would strengthen reliability and validity.

Think critically

Beyond code reuse, what other aspects of the verification process can be standardized or made more efficient to further reduce development time and cost?

Design Principles

"Design for Verification Reuse: Verification components should be architected for modularity and adaptability to facilitate their application across various design contexts and projects."

The complexity of modern integrated circuits necessitates robust verification processes. By adopting reusable design patterns for verification environments, design teams can accelerate product cycles, reduce development expenses, and improve the overall quality and reliability of complex electronic systems.

What This Means for Your Design

Making testing code for computer chips reusable saves a lot of time and money when making new chips.

How to use in your project

1.This research highlights the importance of efficient verification in product development, which can be a factor in evaluating the commercial viability of a design project.

Add to My Project

Quick Cite

Paragraph starter

The challenge of efficient verification in complex system development is significant, with studies indicating that verification can consume up to 75% of design effort. Implementing reusable verification methodologies, as explored in research on System on Chip (SOC) development, offers a practical approach to mitigate these challenges, leading to reduced time-to-market and lower development costs through code reuse across different design stages and IP configurations.

Source

International Journal of VLSI Design & Communication Systems

Advanced Verification Methodology for Complex System on Chip Verification

journal · 2015

View source

Questions About This Research

What does the research say about reusable test bench methodology slashes soc verification time by up to 75%?: Adopt a strategy of building verification environments with reusability as a core principle, enabling components to be leveraged across multiple projects and design stages to accelerate development and reduce costs. Evidence: International Journal of VLSI Design & Communication Systems (2015).
Why does "Reusable test bench methodology slashes SOC verification time by up to 75%" matter for design?: The complexity of modern integrated circuits necessitates robust verification processes. By adopting reusable design patterns for verification environments, design teams can accelerate product cycles, reduce development expenses, and improve the overall quality and reliability of complex electronic systems.
How can designers apply this research?: Adopt a strategy of building verification environments with reusability as a core principle, enabling components to be leveraged across multiple projects and design stages to accelerate development and reduce costs.
What were the main findings?: Verification effort can account for 75% of the total design effort for complex SOCs.. A reusable test bench methodology can significantly decrease time to market.. Code reuse across design levels (sub-block, block, top-level) leads to cost savings.. Intelligent verification approaches are crucial for managing complexity.
What research method was used?: Methodology Development and Case Study.
How strong is the evidence?: Evidence strength is rated Strong effect, based on a 2015 journal from International Journal of VLSI Design & Communication Systems.
What should I do differently in my next project?: When designing a new complex system, consider creating a library of standardized verification modules that can be easily integrated and adapted for different sub-systems and future projects.
What are the limitations?: The effectiveness of the methodology may depend on the specific SOC architecture and the complexity of the design IP. The initial investment in developing reusable components might be significant.