Short answer

Integrate scan chain extraction as a routine step in the ASIC production workflow to generate a verifiable schematic for security audits and to mitigate risks associated with hardware tampering.

Field: Commercial Production
Source: Advances in computer science research (2015)
Method: Formal verification and hardware simulation
Evidence: Strong effect

Leveraging scan chain technology, a standard design-for-testability (DFT) method, allows for the programmatic extraction of an ASIC's schematic, crucial for security verification. This commercial production research insight is drawn from a 2015 study published in Advances in computer science research. Using Formal verification and hardware simulation, researchers explored how this design variable affects real-world outcomes. The key design takeaway: Integrate scan chain extraction as a routine step in the ASIC production workflow to generate a verifiable schematic for security audits and to mitigate risks associated with hardware tampering.

Study

Commercial ProductionHigh ImpactStrong effect

Scan Chain Integration Enables Schematic Verification for ASIC Security

Leveraging scan chain technology, a standard design-for-testability (DFT) method, allows for the programmatic extraction of an ASIC's schematic, crucial for security verification.

Advances in computer science research · 2015

Key Findings

01Scan chain technology can be adapted to extract ASIC schematics.
02The extracted schematic can serve as a Trojan-free reference for security analysis.
03Formal verification and hardware simulation confirm the validity of the approach.

Application

Design takeaway

Integrate scan chain extraction as a routine step in the ASIC production workflow to generate a verifiable schematic for security audits and to mitigate risks associated with hardware tampering.

How to apply

During the ASIC development cycle, implement a procedure to extract the netlist/schematic via the scan chain after fabrication and compare it against the intended design specifications to detect anomalies.

Project actions

01Consider how built-in testing mechanisms in electronic components can be repurposed for security analysis.
02Explore the use of simulation tools to model the extraction process and verify its output.

Method & Evidence

AimCan scan chain technology be utilized to reliably extract an ASIC's schematic for security verification purposes?

MethodFormal verification and hardware simulation

ProcedureThe proposed approach uses the scan chain, a common DFT technique, to extract the schematic of an Application Specific Integrated Circuit (ASIC). This extracted schematic is then verified through formal methods and hardware simulations to ensure its accuracy and utility for detecting hardware Trojans.

ContextApplication-Specific Integrated Circuit (ASIC) design and manufacturing, hardware security

Variables

IVUse of scan chain technology for schematic extraction

DVAccuracy and utility of the extracted ASIC schematic for security verification (e.g., Trojan detection)

CVASIC design complexity, scan chain implementation details, formal verification and simulation environments

Strengths & Limitations

Strengths

+Addresses a critical security concern in hardware design.
+Leverages existing, widely adopted DFT technology.
+Provides a practical, verifiable method.

Limitations

The complexity of implementing scan chain extraction and verification can be high. The availability and compatibility of specific EDA (Electronic Design Automation) tools may also be a constraint.

Reliability & validity

The study's reliability is supported by formal verification and hardware simulation. Validity is established by demonstrating the practical application of the extracted schematic for security purposes (Trojan detection).

Think critically

To what extent does the complexity of modern ASICs impact the feasibility and accuracy of schematic extraction via scan chains for security analysis?

Design Principles

"Utilize built-in testability features for design verification and security assurance."

Ensuring the integrity of an ASIC's design is paramount in commercial production, especially against hardware Trojans. This method provides a reliable way to generate a reference schematic, independent of potentially compromised design files, thereby enhancing security and trust in the manufacturing process.

What This Means for Your Design

This research shows how a special testing feature in computer chips (scan chain) can be used to get a blueprint (schematic) of the chip. This blueprint can then be checked to make sure no one has secretly added bad code (hardware Trojan) to the chip.

How to use in your project

1.Reference this study when discussing methods for verifying the security and authenticity of electronic components in your design project.

Add to My Project

Quick Cite

Paragraph starter

The research by Chen, Liu, and Li (2015) proposes a novel method for obtaining an Application-Specific Integrated Circuit (ASIC) schematic by utilizing scan chain technology, a standard design-for-testability (DFT) feature. This approach offers a way to generate a trusted schematic for security verification, particularly for detecting hardware Trojans, without requiring a pre-verified Trojan-free instance. The method's validity was confirmed through formal verification and hardware simulation, highlighting its potential to enhance security assurance in commercial production.

Source

Advances in computer science research

A Method of Obtaining ASIC Schematic Using Scan Chain

journal · 2015

View source

Questions About This Research

What does the research say about scan chain integration enables schematic verification for asic security?: Integrate scan chain extraction as a routine step in the ASIC production workflow to generate a verifiable schematic for security audits and to mitigate risks associated with hardware tampering. Evidence: Advances in computer science research (2015).
Why does "Scan Chain Integration Enables Schematic Verification for ASIC Security" matter for design?: Ensuring the integrity of an ASIC's design is paramount in commercial production, especially against hardware Trojans. This method provides a reliable way to generate a reference schematic, independent of potentially compromised design files, thereby enhancing security and trust in the manufacturing process.
How can designers apply this research?: Integrate scan chain extraction as a routine step in the ASIC production workflow to generate a verifiable schematic for security audits and to mitigate risks associated with hardware tampering.
What were the main findings?: Scan chain technology can be adapted to extract ASIC schematics.. The extracted schematic can serve as a Trojan-free reference for security analysis.. Formal verification and hardware simulation confirm the validity of the approach.
What research method was used?: Formal verification and hardware simulation.
How strong is the evidence?: Evidence strength is rated Strong effect, based on a 2015 journal from Advances in computer science research.
What should I do differently in my next project?: During the ASIC development cycle, implement a procedure to extract the netlist/schematic via the scan chain after fabrication and compare it against the intended design specifications to detect anomalies.
What are the limitations?: The effectiveness may depend on the specific scan chain implementation and the complexity of the ASIC. The process might require specialized tools and expertise.